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4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
Preliminary Technical Data
Features
PLL generated (32-192kHz) or direct master clock Low EMI design 109 dB DAC/ 107dB ADC Dynamic Range and SNR -94dB THD+N Single 3.3V Supply Tolerance for 5V logic inputs Supports 24-bits and 8 kHz - 192 kHz sample rates Differential ADC input Single-ended or Differential DAC output versions Log volume control with "auto-ramp" function Hardware and software controllable clickless mute Software and hardware power-down Right justified, left justified, I2S and TDM Modes Master and slave modes up to 16 channel in/out 48-lead LQFP or 64-lead LQFP plastic package
AD1935/AD1936/AD1937/AD1938/AD1939
Applications
Automotive audio systems Home theater systems Set-top boxes Digital audio effects processors
GENERAL DESCRIPTION
The AD193X family are high performance, single-chip codecs that provide 4 ADCs with differential input and 8 DACs with either single-ended or differential output using ADI's patented multibit sigma-delta architecture. An SPI(R) or I2C(R) port is included, allowing a microcontroller to adjust volume and many other parameters. The AD193X family operates from 3.3V digital and analog supplies. The AD193X is available in a 48-lead (SE output) or 64-lead (differential output) LQFP package. The AD193X is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive master clock from L-R clock, the AD193X eliminates the need for a separate high frequency master clock. It can also be used with a suppressed bit clock. The D-A and A-D converters are designed using the latest ADI continuous time architectures to further minimize EMI. By using 3.3V supplies, power consumption is minimized, further reducing emissions.
Functional Block Diagram
Digital Audio Input/Output
AD193X
Serial Data Port
DAC DAC ADC SDATAOUT SDATAIN
Analog Audio Inputs
ADC ADC ADC
Digital Filter
CLOCKS
Digital Filter & Volume Control
DAC DAC DAC DAC DAC DAC
Analog Audio Outputs
Timing Management & Control (Clock & PLL)
Precision Voltage Reference
Control Port SPI / I2C
Control Data Input/Output
Figure 1 Rev. PrI
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
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AD1935/AD1936/AD1937/AD1938/AD1939
AD193X--SPECIFICATIONS
Test Conditions, Unless Otherwise Noted.
Preliminary Technical Data
Performance of all channels is identical (exclusive of the Inter-channel Gain Mismatch and Inter-channel Phase Deviation specifications).
Parameter Supply Voltages (AVDD, DVDD) Case Temperature Master Clock Input Signal Input Sample Rate Measurement Bandwidth Word Width Load Capacitance (Digital Output) Load Current (Digital Output) Input Voltage HI Input Voltage LO
Table 1
Rating 3.3 V 25C 12.288 MHz (48 kHz fS, 256 x fS Mode) 1.000 kHz, 0 dBFS (Full Scale), -1 dBVrms (0.9Vrms) 48 kHz 20 Hz to 20 kHz 24 Bits 50 pF 1 mA or 1.5k to 1/2 DVDD supply 2.0 V 0.8 V
Analog Performance
Parameter ADC Resolution (all ADCs) Dynamic Range (20 Hz to 20 kHz, -60 dB Input)1 No Filter (RMS) With A-Weighted Filter (RMS) With A-Weighted Filter (Avg) Total Harmonic Distortion + Noise (-1 dBFS)1 Full-Scale Input Voltage (Differential) Gain Error Interchannel Gain Mismatch Offset Error Gain Drift Interchannel Isolation CMRR, 100 mV RMS, 1 kHz CMRR, 100 mV RMS, 20 kHz Input Resistance Input Capacitance Input Common-Mode Bias Voltage Dynamic Range (20 Hz to 20 kHz, -60 dB Input)1 No Filter (RMS), Single-ended version With A-Weighted Filter (RMS), Single-ended version With A-Weighted Filter (Avg), Single-ended version No Filter (RMS), Differential version With A-Weighted Filter (RMS), Differential version With A-Weighted Filter (Avg), Differential version Total Harmonic Distortion + Noise (0 dBFS)1 Single-ended version Differential version Full-Scale Output Voltage (Single-ended version) Full-Scale Output Voltage (Differential version) Gain Error Min Typ 24 102 105 107 -92 1.9 -5.0 -0.1 -10 +5.0 +0.1 +10 Max Unit Bits dB dB dB dB V rms % dB mV ppm/C dB dB dB k pF V dB dB dB dB dB dB dB dB V rms (V pp) V rms (V pp) %
ANALOG-TO-DIGITAL CONVERTERS
0 100 -110 70 70 14 10 1.5 101 104 106 104 107 109 -92 -94 0.9 (2.5) 1.8 (5.0) TBD
DIGITAL-TO-ANALOG CONVERTERS
-6%
+6%
1
Total harmonic distortion + noise and dynamic range typical specifications are for two channels active, max/min are all channels active. Rev. PrI | Page 2 of 30
Preliminary Technical Data
Parameter
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Min -0.5 Typ -15 -10 -30 100 0 0.375 95 0.6 100 1.50 1.50 1.50 30 Max +0.5 Unit dB mV mV ppm/C dB Degrees dB dB dB V V V
REFERENCE
Interchannel Gain Mismatch Offset Error, Single-ended version Offset Error, Differential version Gain Drift Interchannel Isolation Interchannel Phase Deviation Volume Control Step Volume Control Range De-emphasis Gain Error Output Resistance at Each Pin Internal Reference Voltage, FILTR External Reference Voltage, FILTR Common-Mode Reference Output, CM
Table 2
0.90
1.80
Crystal Oscillator
Parameter Transconductance
Table 3
Min
Typ 10
Max
Unit mmhos
Digital I/O
Parameter Input Voltage HI (VIH) Input Voltage LO (VIL) Input Leakage (IIH @ VIH = 2.4 V) Input Leakage (IIL @ VIL = 0.8 V) High Level Output Voltage (VOH) IOH = 4 mA Low Level Output Voltage (VOL) IOL = 4 mA Input Capacitance
Table 4
Min 2.0
Typ
Max 0.8 10 10
DVDD - 0.5 0.5 5
Unit V V A A V V pF
Power Supplies
Parameter Voltage, DVDD Voltage, AVDD Digital Current Digital Current--Power-Down Digital Current--Reset Analog Current Analog Current--Power-Down Analog Current--Reset Operation--All Supplies Operation--Digital Supply Operation--Analog Supply Power-Down--All Supplies 1 kHz 200 mV p-p Signal at Analog Supply Pins 20 kHz 200 mV p-p Signal at Analog Supply Pins
Table 5
Min 3.0 3.0
Supplies
Dissipation
Power Supply Rejection Ratio
Typ 3.3 3.3 56 TBD TBD 74 TBD TBD 429 185 244 TBD TBD TBD
Max 3.6 3.6
Unit V V mA mA mA mA mA mA mW mW mW mW dB dB
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Temperature Range
Parameter Specifications Guaranteed Functionality Guaranteed Storage Min -40 -40 -65
Table 6
Preliminary Technical Data
Typ 25
Max +105 +125 +150
Unit C Case C Ambient C Case C
Digital Filters
Mode Parameter Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay
Table 7
Factor 0.4375 fS 0.5 fS 0.5625 fS
Min
ADC DECIMATION FILTER
All Modes, Typ @ 48 kHz
Typ 21 0.015 24 27 479 22
Max
79 22.9844/ fS 0.4535 fS 0.5 fS 0.5465 fS 70 25/ fS 0.3646 fS 0.5 fS 0.6354 fS 70 11/ fS 0.3646 fS 0.5 fS 0.6354 fS 70 8/ fS 42 115 70 0.1 96 122 521 35 0.05 48 61
0.01 24 26
48 kHz Mode, Typ @ 48 kHz
DAC INTERPOLATION FILTER
96 kHz Mode, Typ @ 96 kHz
192 kHz Mode, Typ @ 192 kHz
Unit kHz dB kHz kHz dB s kHz dB kHz kHz dB s kHz dB kHz kHz dB s kHz dB kHz kHz dB s
Timing Specifications
Parameter tMH tML tMCLK fMCLK tMH tML tMCLK fMCLK tPDR tPDRR SPI PORT tCCH tCCL tCCP MCLK High MCLK Low MCLK Period MCLK Frequency MCLK High MCLK Low MCLK Period MCLK Frequency PD/RST Low PD/RST Recovery CCLK High CCLK Low CCLK Period
Rev. PrI | Page 4 of 30
MASTER CLOCK AND RESET
Comments PLL Mode PLL Mode PLL Mode, 256 fS reference PLL Mode, 256 fS reference Direct 512 fS Mode Direct 512 fS Mode Direct 512 fS Mode Direct 512 fS Mode Reset to Active Output
Min 15 15 73 6.9 15 15 36 TBD TBD TBD TBD 50
Max
146 13.8
27.6
Unit ns ns ns MHz ns ns ns MHz ns tMCLK ns ns ns
Preliminary Technical Data
Parameter fCCLK tCDS tCDH tCLS tCLH tCLH tCOE tCOD tCOH tCOTS fSCL tSCLH tSCLL tSCS I2C PORT Start Condition tSCH tDS tSCR tSCF tSDR tSDF tSCS tDBH tDBL fDB tDLS tDLH tDLS tDDS tDDH tABH tABL fDB tALS tALH tALS tABDD tAXDS tAXDH tDXDD tXBH tXBL fXB tDLS tDLH CCLK Frequency CDATA Setup CDATA Hold CLATCH Setup CLATCH Hold CLATCH High COUT Enable COUT Delay COUT Hold COUT Three-State SCL Clock Frequency SCL High SCL Low Setup Time Hold Time Data Setup Time SCL Rise Time SCL Fall Time SDA Rise Time SDA Fall Time Setup Time DBCLK High DBCLK Low DBCLK Frequency DLRCLK Setup DLRCLK Hold DLRCLK Skew DSDATA Setup DSDATA Hold ABCLK High ABCLK Low ABCLK Frequency ALRCLK Setup ALRCLK Hold ALRCLK Skew ASDATA Delay AAUXDATA Setup AAUXDATA Hold DAUXDATA Delay AUXBCLK High AUXBCLK Low AUXBCLK Frequency AUXLRCLK Setup AUXLRCLK Hold
AD1935/AD1936/AD1937/AD1938/AD1939
Comments To CCLK Rising From CCLK Rising To CCLK Rising From CCLK Falling From CCLK Falling From CCLK Falling From CCLK Falling From CCLK Falling Min TBD TBD TBD TBD TBD TBD TBD TBD TBD 400 0.6 1.3 0.6 0.6 100 300 300 300 300 0.6 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD To AUXBCLK Rising From AUXBCLK Rising TBD TBD Max 20 Unit MHz ns ns ns ns ns ns ns ns ns kHz S S S S ns ns ns ns ns S ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Relevant for Repeated Start Condition After this period the 1st clock is generated
Stop Condition
Slave Mode DAC SERIAL PORT Master Mode
To DBCLK Rising From DBCLK Rising From DBCLK Falling To DBCLK Rising From DBCLK Rising
TBD
Slave Mode ADC SERIAL PORT Master Mode
To ABCLK Rising From ABCLK Rising From ABCLK Falling From ABCLK Falling To AUXBCLK Rising From AUXBCLK Rising From AUXBCLK Falling
TBD TBD
AUXILIARY INTERFACE
Table 8
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ABSOLUTE MAXIMUM RATINGS
Preliminary Technical Data
Package Characteristics
Parameter Analog (AVDD) Digital (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Case Temperature (Operating)
Table 9
Min -0.3 -0.3 -0.3 -0.3 -40
Max +3.6 +3.6 20 AVDD + 0.3 DVDD + 0.3 +125
Unit V V mA V V C
Parameter JA (Thermal Resistance [Junction to Ambient]), 48-lead LQFP JC (Thermal Resistance [Junction to Case]), 48-lead LQFP JA (Thermal Resistance [Junction to Ambient]), 64-lead LQFP JC (Thermal Resistance [Junction to Case]), 64-lead LQFP
Min
Typ 50.1 17 47 11.1
Max
Unit C/W C/W C/W C/W
Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note: Characteristics are for a 4-layer board Table 10
Rev. PrI | Page 6 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
Figure 2. ADC Passband Filter Response, 48 kHz
Figure 3. ADC Stopband Filter Response, 48 kHz
Figure 4. DAC Passband Filter Response, 48 kHz
Figure 5. DAC Stopband Filter Response, 48 kHz
Figure 6. DAC Passband Filter Response, 96 kHz
Figure 7. DAC Stopband Filter Response, 96 kHz
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Preliminary Technical Data
Figure 8. DAC Passband Filter Response, 192 kHz
Figure 9. DAC Stopband Filter Response, 192 kHz
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Preliminary Technical Data FUNCTIONAL OVERVIEW
ADCs
There are four ADC channels in the AD193X configured as two stereo pairs with differential inputs. The ADCs can operate at a nominal sample rate of 48, 96 , or 192 kHz. The ADCs include onboard digital anti-aliasing filters with 79 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz modes). Digital outputs are supplied through two serial data output pins (one for each stereo pair) and a common frame (ALRCLK) and bit (ABCLK) clock. Alternatively, one of the TDM modes may be used to access up to 16 channels on a single TDM data line. The ADCs must be driven from a differential signal source for best performance. The input pins of the ADCs connect to internal switched capacitors. To isolate the external driving op amp from the "glitches" caused by the internal switched capacitors, each input pin should be isolated by using a series-connected external 100 resistor together with a 1 nF capacitor connected from each input to ground. This capacitor must be of high quality; for example, ceramic NPO or polypropylene film. The differential inputs have a nominal common-mode voltage of 1.5V. The voltage at the common-mode reference pin, CM can be used to bias external op amps to buffer the input signals (see the Power Supply and Voltage Reference section). The inputs can also be AC coupled and do not need an external DC bias to CM. A digital high-pass filter can be switched in line with the ADCs under serial control to remove residual dc offsets. It has a 1.4 Hz, 6 dB per octave cutoff at a 48 kHz sample rate. The cutoff frequency will scale directly with sample frequency.
AD1935/AD1936/AD1937/AD1938/AD1939
rate or low bandwidth may cause high frequency noise and tones to fold down into the audio band; care should be exercised in selecting these components. The voltage at the common-mode reference pin, CM can be used to bias the external op amps that buffer the output signals (see the Power Supply and Voltage Reference section).
Clock Signals
The on-chip Phase Locked Loop (PLL) can be selected to use as its reference the input sample rate from either of the LRCLK pins or 256, 384, 512, or 768 times the sample rate, referenced to 48kHz mode, from the MCLKI pin. The default at power-up is 256 x fS from MCLKI. In 96 kHz mode, the master clock frequency will stay at the same absolute frequency so the actual multiplication rate will be divided by 2. In 192 kHz mode, the actual multiplication rate will be divided by 4. For example, if the AD193X is programmed in 256 x fS mode, the frequency of the master clock input would be 256 x 48 kHz = 12.288 MHz. If the AD193X is then switched to 96 kHz operation (by writing to the SPI or I2C port), the frequency of the master clock should remain at 12.288 MHz, which is now 128 x fS. In 192kHz mode, this would be 64 x fS. The internal clock for the ADCs is 256 x fS for all clock modes. The internal clock for the DACs is 512 x fS (48 kHz mode), 256 x fS (96 kHz mode), or 128 x fS (192 kHz mode). By default, the on-board PLL is used to generate this internal master clock from an external clock. A direct 512 x fS ( referenced to 48 kHz mode) master clock can be used for either the ADCs or DACs if selected in PLL and Clock Control Register 1. Note that it is not possible to use a direct clock for the ADCs set to 192kHz mode. It is required that the on-chip PLL be used in this mode. The PLL can be powered down in PLL and Clock Control Register 0. To ensure reliable locking when changing PLL modes or if the reference clock may be unstable at power-on, the PLL should be powered down and then powered back up when the reference clock is stable. The internal MCLK can be disabled in PLL and Clock Control Register 0 to reduce power dissipation when the AD193X is idle. The clock should be stable before it is enabled. Unless a standalone mode is selected (see Serial Control Port), the clock is disabled by reset and must be enabled by writing to the SPI or I2C port for normal operation. To maintain the highest performance possible, it is recommended that the clock jitter of the internal master clock signal be limited to less than 300 ps rms TIE (time interval error). Even at these levels, extra noise or tones may appear in the DAC outputs if the jitter spectrum contains large spectral peaks. If the internal PLL is not being used, it is highly recommended that an independent crystal
DACs
The AD193X DAC channels are arranged as four stereo pairs giving eight analog outputs, either single-ended for minimum external components or differential for improved noise and distortion performance. The DACs include on-board digital reconstruction filters with 70 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 4 (48 kHz or 96 kHz modes) or 2 (192 kHz mode). Each channel has its own independently programmable attenuator, adjustable in 255 0.375 dB steps. Digital inputs are supplied through four serial data input pins (one for each stereo pair) and a common frame (DLRCLK) and bit (DBCLK) clock. Alternatively, one of the TDM modes may be used to access up to 16 channels on a single TDM data line. Each output pin has a nominal common-mode dc level of 1.5V and swings 1.27 V for a 0 dBFS digital input signal. A single op amp third order external low-pass filter is recommended to remove high frequency noise present on the output pins, as well as to provide differential-to-single-ended conversion in the case of the differential output part. Note that the use of op amps with low slew
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AD1935/AD1936/AD1937/AD1938/AD1939
oscillator generate the master clock. In addition, it is especially important that the clock signal should not be passed through an FPGA, CPLD, or other large digital chip (such as a DSP) before being applied to the AD193X. In most cases, this will induce clock jitter due to the sharing of common power and ground connections with other unrelated digital output signals. When the PLL is used, jitter in the reference clock will be attenuated above a certain frequency depending on the loop filter.
Preliminary Technical Data
permits programming and reading back the internal control registers for the ADCs, DACs, and clock system. There is also a stand-alone mode available for operation without serial control, configured at reset using the serial control pins. All registers are set to default except Internal MCLK Enable is set to 1 and ADC BCLK and LRCLK Master/Slave is set by COUT/SDA. Refer to Table 10 for details. ADC Clocks: Slave Master
CIN/ADR0 COUT/SDA CCLK/SCL
CLATCH/ADR1
Reset and Power-Down
Reset will set all the control registers to their default settings. To avoid pops, reset does not power down the analog outputs. After reset is de-asserted, an initialization routine will run inside the AD193X. This initialization lasts for approximately XX MCLKs. The power-down bits in the PLL and Clock Control 0, DAC Control 1, and ADC Control 1 registers will power down the respective sections. All other register settings are retained.
0 0
0 1
0 0
0 0
Table 11. Stand-alone Mode Selection
Serial Control Port
The AD193X has an SPI or I2C compatible control port that
tCLS
CLATCH
The SPI control port of the AD1938 and AD1939 is a 4-wire serial control port. The format is similar to the Motorola SPI format except the input data-word is 24 bits wide. The serial bit clock and latch may be completely asynchronous to the sample rate of the ADCs and DACs. Figure 10 shows the format of the SPI signal. The first byte is a global address with a read/write bit. For the AD193X the address is 0x04, shifted left 1 bit due to the R/W bit. The second byte is the AD193X register address and the third byte is the data.
tCLH tCOTS
tCCP
tCCH tCCL
CCLK
tCDS tCDH
CIN D15 D14 D9 D8 D0
COUT
tCOE
D9
D8
D0
tCOD
Figure 10. Format of SPI Signal
The I2C interface of the AD1936 and AD1937 is a two wire interface consisting of a clock line, SCL and a data line, SDA. SDA is bidirectional and the AD1936 and AD1937 will drive SDA either to acknowledge the master, ACK, or to send data during a read operation. The SDA pin for the I2C port is an open drain collector and requires a 1K pullup resistor. A write or read access occurs when the SDA line is pulled low while the SCL line is high indicated by START in the timing diagrams. SDA is only allowed to change when SCL is low except when a START or STOP condition occurs as shown in figures 3 and 4. The first eight bits of the access consist of the device address and the R/W bit. The device address consists of an internal built-in address (0x04) and two address pins, AD1 and AD0. The two address pins allow up to four AD1936s and AD1937s to be used in a system. Initiating a write operation to the AD1936 and AD1937 involves sending a START condition and then sending the device address with the R/W set low. The AD1936 and AD1937 will respond by issuing an ACK to indicate that it has been addressed. The user then sends a second frame telling the
AD1936 and AD1937 which register is required to be written to. Another ACK is issued by the AD1936 and AD1937. Finally the user can send another frame with the 8 data bits required to be written to the register. A third ACK is issued by the AD1936 and AD1937 after which the user can send a STOP condition to complete the data transfer. A read operation requires that the user first write to the AD1936 and AD1937 to point to the correct register and then read the data. This is achieved by sending a START condition followed by the device address frame, with R/W low, and then the register address frame. Following the ACK from the AD1936 and AD1937 the user must issue a REPEATED START condition. This is identical to a START condition. The next frame is the device address with R/W set high. On the next frame the AD1936 and AD1937 will output the register data on the SDA line. A STOP condition completes the read operation. Figure 3 and Figure 4 show examples of writing to and reading from the DAC 1 Left Volume Register (address = 0x06)
Rev. PrI | Page 10 of 30
Preliminary Technical Data
SCK
AD1935/AD1936/AD1937/AD1938/AD1939
SDA START BY MASTER
0
0
0
0
1
AD1
AD0
R/W ACK. BY AD193X
0
0
0
0
0
1
1
0 ACK. BY AD193X
FRAME 1 CHIP ADDRESS BYTE
FRAME 2 REGISTER ADDRESS BYTE
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY STOP BY AD193X MASTER
FRAME 3 DATA BYTE TO AD193X
Figure 11. Format of I2C Write
SCL
SDA START BY MASTER
0
0
0
0
1
AD1
AD0
R/W ACK. BY AD193X
0
0
0
0
0
1
1
0 ACK. BY AD193X
FRAME 1 CHIP ADDRESS BYTE
FRAME 2 REGISTER ADDRESS BYTE
SDA (Continued)
0
0
0
0
1
AD1
AD0
R/W ACK. BY AD193X
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY AD193X
REPEATED START BY MASTER
FRAME 3 CHIP ADDRESS BYTE
FRAME 4 REGISTER DATA
STOP BY MASTER
Figure 12. Format of I2C Read
Power Supply and Voltage Reference
The AD193X is designed for 3.3 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the pins as possible, to minimize noise pickup. A bulk aluminum electrolytic capacitor of at least 22 F should also be provided on the same PC board as the codec. For critical applications, improved performance will be obtained with separate supplies for the analog and digital sections. If this is not possible, it is recommended that the analog and digital supplies be isolated by means of a ferrite bead in series with each supply. It is important that the analog supply be as clean as possible. The AD1935 (64-pin single-ended version), and the AD1939 and AD1937 (64-pin differential versions) include a 3.3V regulator driver which requires only an external pass transistor and bypass capacitors to make a 5V to 3.3V regulator. If the regulator driver is not used, VSUPPLY, VDRIVE, and VSENSE should be connected to DGND. All digital inputs are compatible with TTL and CMOS levels. All
outputs are driven from the 3.3 V DVDD supply and are compatible with TTL and 3.3 V CMOS levels. The ADC and DAC internal voltage reference VREF is brought out on FILTR and should be bypassed as close as possible to the chip, with a parallel combination of 10 F and 100 nF. Any external current drawn should be limited to less than 50 A. The internal reference can be disabled in PLL and Clock Control Register 1 and FILTR driven from an external source. This can be used to scale the DAC output to a power amplifier's clipping level based on its power supply voltage. The ADC input gain will also vary by the inverse ratio. The total gain from ADC input to DAC output will stay constant. The CM pin is the internal common-mode reference. It should be bypassed as close as possible to the chip, with a parallel combination of 10 F and 100 nF. This voltage may be used to bias external op amps to the common-mode voltage of the input and output signal pins. The output current should be limited to less than 0.5 mA source and 2 mA sink.
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803-0040
SCL (Continued)
803-0039
SCK (CONTINUED)
AD1935/AD1936/AD1937/AD1938/AD1939
Serial Data Ports--Data Format
The eight DAC channels output or accept a common serial bit clock and left-right framing clock to clock in the serial data. The four ADC channels output or accept a common serial bit clock and leftright framing clock to clock out the data. The clock signals are all synchronous with the sample rate. In the AUX Modes, set in ADC Control 1 and DAC Control 0, the DACs use the ADC serial bit clock and left-right clock as the DAC clock pins are used for the auxiliary ADC/DAC serial clocks. The ADC and DAC serial data modes default to I2S. The ports can also be programmed for left-justified, right-justified and TDM modes. The word width is 24 bits by default and can be programmed for 16 or 20 bits. The normal TDM mode can be daisy-chained with a second AD193X and will support 16 channels
Preliminary Technical Data
at 48 kHz, 8 channels at 96 kHz or 4 channels at 192 kHz. There is also a dual-line TDM mode to support 8 channels at 192 kHz. The special auxiliary modes are provided to allow two external stereo ADCs and/or two external stereo DACs to be interfaced with the AD193X to provide up to 8 in/12 out operation or 2 AD193Xs to be chained for up to 16 in/16 out operation. These modes provide a glueless interface to a single SHARC serial port, allowing the DSP to access up to 16 channels of analog I/O. In these modes many pins are redefined, see table 10. See Figure 18 for details of these modes. The following figures show the serial mode formats.
LRCLK BCLK SDATA MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
LSB
LEFT JUSTIFIED MODE--16 BITS TO 24 BITS PER CHANNEL
LRCLK BCLK SDATA MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
LSB
I2S MODE--16 BITS TO 24 BITS PER CHANNEL
LRCLK BCLK SDATA MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
LSB
RIGHT JUSTIFIED MODE--SELECT NUMBER OF BITS PER CHANNEL
LRCLK BCLK SDATA MSB LSB MSB LSB
DSP MODE--16 BITS TO 24 BITS PER CHANNEL 1/fS NOTES 1. DSP MODE DOES NOT IDENTIFY CHANNEL 2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH IS 2 x fS 3. BCLK FREQUENCY IS NORMALLY 64 x LRCLK BUT MAY BE OPERATED IN BURST MODE
Figure 13. Stereo Serial Modes
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Preliminary Technical Data
tDBH
DBCLK
AD1935/AD1936/AD1937/AD1938/AD1939
tDBP tDBL tDLS tDLH
DLRCLK
DSDATA LEFT-JUSTIFIED MODE
tDDS
MSB MSB-1
tDDH tDDS
MSB
DSDATA I2 S-JUSTIFIED MODE
tDDH tDDS
MSB
DSDATA RIGHT-JUSTIFIED MODE
tDDS
LSB
tDDH
tDDH
Figure 14. DAC Serial Timing
tABH
ABCLK
tABP tABL tALS tALH
ALRCLK
tABDD
ASDATA LEFT-JUSTIFIED MODE MSB MSB-1
tABDD
ASDATA I2 S-JUSTIFIED MODE MSB
tABDD
ASDATA RIGHT-JUSTIFIED MODE MSB LSB
Figure 15. ADC Serial Timing
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AD1935/AD1936/AD1937/AD1938/AD1939
LRCLK 256 BCLKs BCLK 32 BCLKs SLOT 1 LEFT 1 SLOT 2 SLOT 3 RIGHT 1 LEFT 2 SLOT 4 SLOT 5 RIGHT 2 SLOT 6
Preliminary Technical Data
DATA
SLOT 7
SLOT 8
LRCLK BCLK MSB MSB-1 MSB-2 DATA
Figure 16. ADC TDM (8-channel I2Smode )
LRCLK 256 BCLKs BCLK 32 BCLKs SLOT 1 LEFT 1 SLOT 2 SLOT 3 RIGHT 1 LEFT 2 SLOT 4 SLOT 5 RIGHT 2 LEFT 3 SLOT 6 SLOT 7 RIGHT 3 LEFT 4 SLOT 8 RIGHT 4
DATA
LRCLK BCLK MSB MSB-1 MSB-2 DATA
Figure 17. DAC TDM (8-channel I2S mode)
FSTDM
BCLK TDM
MSB TDM MSB TDM
8TH CH
TDM INTERFACE
ASDATA1 TDM (OUT) ASDATA
1ST CH
ADC L1
ADC R1
ADC L2
ADC R2
AUX ADC L1
AUX ADC R1
AUX ADC L2
AUX ADC R2
32
MSB TDM MSB TDM
8TH CH
DSDATA1 TDM (IN) DSDATA1
1ST CH
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
32
AUX LRCLK (FROM AUX ADC 1)
AUX - I2S INTERFACE
LEFT
RIGHT
AUX BCLK (FROM AUX ADC 1) AUX DATA IN 1 (FROM AUX ADC 1)
I2S - MSB LEFT
I2 S - MSB RIGHT
AUX DATA IN 2 (FROM AUX ADC 2)
I2S - MSB LEFT
I2 S - MSB RIGHT
AUX BCLK FREQUENCY IS 64 x FRAME-RATE; TDM BCLK FREQUENCY IS 256 x FRAME-RATE.
Figure 18. AUX 256 Mode Timing (Note that the Clocks Are Not to Scale)
Rev. PrI | Page 14 of 30
Preliminary Technical Data
Pin Function Changes in TDM and AUX Modes
Pin Name ASDATA1 ASDATA2 DSDATA1 DSDATA2 DSDATA3 DSDATA4 ALRCLK ABCLK DLRCLK DBCLK Stereo Modes ADC1 Data Out ADC2 Data Out DAC1 Data In DAC2 Data In DAC3 Data In DAC4 Data In ADC LRCLK In/Out ADC BCLK In/Out DAC LRCLK In/Out DAC BCLK In/Out
AD1935/AD1936/AD1937/AD1938/AD1939
TDM Modes ADC TDM Data Out ADC TDM Data In DAC TDM Data In DAC TDM Data Out DAC TDM Data In 2 (dual-line mode) DAC TDM Data Out 2 (dual-line mode) ADC TDM Frame Sync In/Out ADC TDM BCLK In/Out DAC TDM Frame Sync In/Out DAC TDM BCLK In/Out
Table 12
AUX Modes TDM Data Out AUX Data Out 1 (to Ext. DAC 1) TDM Data In AUX Data In 1 (from Ext. ADC 1) AUX Data In 2 (from Ext. ADC 2) AUX Data Out 2 (to Ext. DAC 2) TDM Frame Sync In/Out TDM BCLK In/Out AUX LRCLK In/Out AUX BCLK In/Out
30MHz
FSYNC-TDM (RFS)
SHARC
SHARC IS RUNNING IN SLAVE MODE (INTERRUPT-DRIVEN)
TFS (NC)
RxDATA
RxCLK
TxCLK
TxDATA
12.288MHz
LRCLK AUX ADC 1 BCLK DATA MCLK DBCLK DLRCLK LRCLK AUX ADC 2 BCLK DATA MCLK DSDATA2 DSDATA3 MCLK ASDATA1 ALRCLK ABCLK DSDATA1
LRCLK BCLK DATA MCLK AUX DAC 1
AD193X
TDM MASTER AUX MASTER ASDATA2 DSDATA4
LRCLK BCLK DATA MCLK AUX DAC 2
Figure 19. Example of AUX Mode Connection to SHARC (AD193X as TDM Master/AUX Master shown)
Rev. PrI | Page 15 of 30
AD1935/AD1936/AD1937/AD1938/AD1939
PIN FUNCTION DESCRIPTIONS
48-Lead LQFP Plastic Package - AD1936, AD1938
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 In/Out I I I I I O O O O I I I I I I I I/O I/O O O I/O I/O O I I I I O O O O I I I O I I O I I I I I I I I O I Mnemonic AGND MCLKI/XI MCLK/XO AGND AVDD OL3 OR3 OL4 OR4
PD/RST
Preliminary Technical Data
DSDATA4 DGND DVDD DSDATA3 DSDATA2 DSDATA1 DBCLK DLRCLK ASDATA2 ASDATA1 ABCLK ALRCLK CIN/ADR0 COUT/SDA DGND CCLK/SCL
CLATCH/ADR1
OL1 OR1 OL2 OR2 AGND AVDD AGND FILTR AGND AVDD CM ADC1LP ADC1LN ADC1RP ADC1RN ADC2LP ADC2LN ADC2RP ADC2RN LF AVDD
Description Analog Ground. Master Clock Input/ Crystal Oscillator Input. Master Clock Output/ Crystal Oscillator Output. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. DAC 3 Left Output. DAC 3 Right Output. DAC 4 Left Output. DAC 4 Right Output. Power-Down Reset (Active Low). DAC Input 4 (Input to DAC 4 L and R). Digital Ground. Digital Power Supply. Connect to digital 3.3 V supply. DAC Input 3 (Input to DAC 3 L and R). DAC Input 2 (Input to DAC 2 L and R). DAC Input 1 (Input to DAC 1 L and R). Bit Clock for DACs. LR Clock for DACs. ADC Serial Data Output 2 (ADC 2 L and R). ADC Serial Data Output 1 (ADC 1 L and R). Bit Clock for ADCs. LR Clock for ADCs. Control Data Input (SPI)/Address 0 (I2C). Control Data Output (SPI)/Serial Data (I2C). Digital Ground. Control Clock Input (SPI)/Serial Clock (I2C). Latch Input for Control Data (SPI)/Address 1 (I2C). DAC 1 Left Output. DAC 1 Right Output. DAC 2 Left Output. DAC 2 Right Output. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. Analog Ground. Voltage Reference Filter Capacitor Connection. Bypass with 10 F||100 nF to AGND. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. Common Mode Reference Filter Capacitor Connection. Bypass with 10 F||100 nF to AGND. ADC1 Left Positive Input. ADC1 Left Negative Input. ADC1 Right Positive Input. ADC1 Right Negative Input. ADC2 Left Positive Input. ADC2 Left Negative Input. ADC2 Right Positive Input. ADC2 Right Negative Input. PLL Loop Filter, Return to AVDD. Analog Power Supply. Connect to analog 3.3 V supply.
Table 13. Pin Function Description--48-Lead LQFP( AD1936, AD1938)
Rev. PrI | Page 16 of 30
Preliminary Technical Data
64-Lead LQFP Plastic Package - AD1937, AD1939
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 In/Out I I I I I O O O O O O O O I I I I I I I I/O I/O Mnemonic AGND MCLKI/XI MCLK/XO AGND AVDD OL3P OL3N OR3P OR3N OL4P OL4N OR4P OR4N
PD/RST
AD1935/AD1936/AD1937/AD1938/AD1939
O O I/O I/O I I/O I I I I O O O O O O O O I I I O I
DSDATA4 DGND DVDD DSDATA3 DSDATA2 DSDATA1 DBCLK DLRCLK VSUPPLY VSENSE VDRIVE ASDATA2 ASDATA1 ABCLK ALRCLK CIN/ADR0 COUT/SDA DVDD DGND CCLK/SCL
CLATCH/ADR1
OL1P OL1N OR1P OR1N OL2P OL2N OR2P OR2N AGND AVDD AGND FILTR AGND
I
AVDD
Description Analog Ground. Master Clock Input/ Crystal Oscillator Input. Master Clock Output/ Crystal Oscillator Output. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. DAC 3 Left Positive Output. DAC 3 Left Negative Output. DAC 3 Right Positive Output. DAC 3 Right Negative Output. DAC 4 Left Positive Output. DAC 4 Left Negative Output. DAC 4 Right Positive Output. DAC 4 Right Negative Output. Power-Down Reset (Active Low). DAC Input 4 (Input to DAC 4 L and R). Digital Ground. Digital Power Supply. Connect to digital 3.3 V supply. DAC Input 3 (Input to DAC 3 L and R). DAC Input 2 (Input to DAC 2 L and R). DAC Input 1 (Input to DAC 1 L and R). Bit Clock for DACs. LR Clock for DACs. +5V Input to Regulator, Emitter of Pass Transistor +3.3V Output of Regulator, Collector of Pass Transistor Drive for Base of Pass Transistor ADC Serial Data Output 2 (ADC 2 L and R). ADC Serial Data Output 1 (ADC 1 L and R). Bit Clock for ADCs. LR Clock for ADCs. Control Data Input (SPI)/Address 0 (I2C). Control Data Output (SPI)/Serial Data (I2C). Digital Power Supply. Connect to digital 3.3 V supply. Digital Ground. Control Clock Input (SPI)/Serial Clock (I2C). Latch Input for Control Data (SPI)/Address 1 (I2C). DAC 1 Left Positive Output. DAC 1 Left Negative Output. DAC 1 Right Positive Output. DAC 1 Right Negative Output. DAC 2 Left Positive Output. DAC 2 Left Negative Output. DAC 2 Right Positive Output. DAC 2 Right Negative Output. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. Analog Ground. Voltage Reference Filter Capacitor Connection. Bypass with 10 F||100 nF to AGND. Analog Ground. No Connect. No Connect. Analog Power Supply. Connect to analog 3.3 V supply.
Rev. PrI | Page 17 of 30
AD1935/AD1936/AD1937/AD1938/AD1939
Pin No. 52 53 54 55 56 57 58 59 60 61 62 63 64 In/Out O I I I I I I I I O I Mnemonic CM ADC1LP ADC1LN ADC1RP ADC1RN ADC2LP ADC2LN ADC2RP ADC2RN LF AVDD
Preliminary Technical Data
Description Common Mode Reference Filter Capacitor Connection. Bypass with 10 F||100 nF to AGND. ADC1 Left Positive Input. ADC1 Left Negative Input. ADC1 Right Positive Input. ADC1 Right Negative Input. ADC2 Left Positive Input. ADC2 Left Negative Input. ADC2 Right Positive Input. ADC2 Right Negative Input. PLL Loop Filter, Return to AVDD. Analog Power Supply. Connect to analog 3.3 V supply. No Connect. No Connect.
Table 14. Pin Function Description--64-Lead LQFP (AD1937, AD1939)
64-Lead LQFP Plastic Package - AD1935
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 In/Out I I I I I O O O O O O O O I I I I I I I I/O I/O Mnemonic AGND MCLKI/XI MCLK/XO AGND AVDD OL3 OR3 OL4 OR4
PD/RST
O O I/O I/O I I/O I I I I
DSDATA4 DGND DVDD DSDATA3 DSDATA2 DSDATA1 DBCLK DLRCLK VSUPPLY VSENSE VDRIVE ASDATA2 ASDATA1 ABCLK ALRCLK CIN COUT DVDD DGND CCLK
CLATCH
Description Analog Ground. Master Clock Input/ Crystal Oscillator Input. Master Clock Output/ Crystal Oscillator Output. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. DAC 3 Left Output. No Connect. DAC 3 Right Output. No Connect. DAC 4 Left Output. No Connect. DAC 4 Right Output. No Connect. Power-Down Reset (Active Low). DAC Input 4 (Input to DAC 4 L and R). Digital Ground. Digital Power Supply. Connect to digital 3.3 V supply. DAC Input 3 (Input to DAC 3 L and R). DAC Input 2 (Input to DAC 2 L and R). DAC Input 1 (Input to DAC 1 L and R). Bit Clock for DACs. LR Clock for DACs. +5V Input to Regulator, Emitter of Pass Transistor +3.3V Output of Regulator, Collector of Pass Transistor Drive for Base of Pass Transistor ADC Serial Data Output 2 (ADC 2 L and R). ADC Serial Data Output 1 (ADC 1 L and R). Bit Clock for ADCs. LR Clock for ADCs. Control Data Input (SPI) Control Data Output (SPI) Digital Power Supply. Connect to digital 3.3 V supply. Digital Ground. Control Clock Input (SPI) Latch Input for Control Data (SPI)
Rev. PrI | Page 18 of 30
Preliminary Technical Data
Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 In/Out O O O O O O O O I I I O I Mnemonic OL1 OR1 OL2 OR2 AGND AVDD AGND FILTR AGND
AD1935/AD1936/AD1937/AD1938/AD1939
I O I I I I I I I I O I
AVDD CM ADC1LP ADC1LN ADC1RP ADC1RN ADC2LP ADC2LN ADC2RP ADC2RN LF AVDD
Description DAC 1 Left Output. No Connect. DAC 1 Right Output. No Connect. DAC 2 Left Output. No Connect. DAC 2 Right Output. No Connect. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. Analog Ground. Voltage Reference Filter Capacitor Connection. Bypass with 10 F||100 nF to AGND. Analog Ground. No Connect. No Connect. Analog Power Supply. Connect to analog 3.3 V supply. Common Mode Reference Filter Capacitor Connection. Bypass with 10 F||100 nF to AGND. ADC1 Left Positive Input. ADC1 Left Negative Input. ADC1 Right Positive Input. ADC1 Right Negative Input. ADC2 Left Positive Input. ADC2 Left Negative Input. ADC2 Right Positive Input. ADC2 Right Negative Input. PLL Loop Filter, Return to AVDD. Analog Power Supply. Connect to analog 3.3 V supply. No Connect. No Connect.
Table 15. Pin Function Description--64-Lead LQFP (AD1935)
PIN CONFIGURATION
ADC2RN ADC2RN ADC2RP ADC1RP ADC2LN ADC1LN AVDD ADC2LP ADC1LP
48 47 46 45 44 43 42 41 40 39 38 37
AGND 1 MCLKI/XI 2 MCLKO/XO 3 AGND 4 AVDD 5 OL3 6 OR3 7 OL4 8 OR4 9 PD/RST 10 DSDATA4 11 DGND 12
13 14 15 16 17 18 19 20 21 22 23 24
AVDD
LF
CM
36 35 34
AGND FILTR AGND AVDD AGND OR2 OL2 OR1 OL1 CLATCH/ADR1 CCLK/SCL DGND
AD193X
TOP VIEW (Not to Scale)
33 32 31 30 29 28
Single-ended Output
Preliminary
DSDATA2 DSDATA1 DVDD DSDATA3 DBCLK DLRCLK ASDATA2 ASDATA1 COUT/SDA ABCLK ALRCLK CIN/ADR0
27 26 25
Figure 20. Single-ended Output 48-Lead LQFP (AD1936, AD1938)
Rev. PrI | Page 19 of 30
AD1935/AD1936/AD1937/AD1938/AD1939
ADC2RN ADC2RN ADC2RP ADC1RP ADC2LN ADC1LN ADC2LP ADC1LP AVDD AVDD CM NC NC NC LF NC
Preliminary Technical Data
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AGND MCLKI/XI MCLKO/XO
1 2 3
48 47 46 45 44
AGND FILTR AGND AVDD AGND
AGND 4 AVDD 5 OL3P 6 OL3N 7 OR3P 8 OR3N 9 OL4P 10 OL4N 11 OR4P 12 OR4N 13 PD/RST 14 DSDATA4 15 DGND 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AD193X
TOP VIEW (Not to Scale)
OR2N 42 OR2P
43 41 40 39 38
Differential Output
OL2N OL2P OR1N OR1P OL1N OL1P CLATCH/ADR1 CCLK/SCL DGND
Preliminary
37 36 35 34 33
DSDATA1 DBCLK
DLRCLK VSUPPLY
ASDATA2
DSDATA3 DSDATA2
ASDATA1
CIN/ADR0
AVDD
Figure 21. Differential Output 64-Lead LQFP (AD1937, AD1939)
ADC2RN ADC2RN ADC2RP ADC1RP ADC2LN ADC1LN ADC2LP AVDD ADC1LP
CM
NC
COUT/SDA
VSENSE
VDRIVE
ABCLK
ALRCLK
DVDD
NC
NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
LF
NC
DVDD
AGND MCLKI/XI MCLKO/XO
1 2 3
48 47 46 45 44
AGND FILTR AGND AVDD AGND
AGND 4 AVDD 5 OL3 6 NC 7 OR3 8 NC 9 OL4 10 NC 11 OR4 12 NC 13 PD/RST 14 DSDATA4 15 DGND 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AD193X
TOP VIEW (Not to Scale)
NC 42 OR2
43 41 40 39 38
Single-ended Output
NC OL2 NC OR1 NC OL1 CLATCH CCLK DGND
Preliminary
37 36 35 34 33
DSDATA1 DBCLK
DLRCLK VSUPPLY
COUT
CIN
DSDATA3 DSDATA2
ASDATA2
ASDATA1
VSENSE
VDRIVE
Figure 22. Single-ended Output Output 64-Lead LQFP (AD1935)
Rev. PrI | Page 20 of 30
ALRCLK
ABCLK
DVDD
DVDD
Preliminary Technical Data APPLICATION CIRCUITS
AD1935/AD1936/AD1937/AD1938/AD1939
Figure 23. Typical ADC Input Filter Circuit
Figure 24. Typical DAC Output Filter Circuit (Single-ended, Non-inverting)
Figure 25. Typical DAC Output Filter Circuit (Single-ended, Inverting)
Figure 26. Typical DAC Output Filter Circuit (Differential)
Rev. PrI | Page 21 of 30
AD1935/AD1936/AD1937/AD1938/AD1939
Preliminary Technical Data
Figure 27. Recommended Loop Filters for LRCLK or MCLK PLL reference.
Figure 28. Recommended 3.3V Regulator Circuit (64-lead versions)
Rev. PrI | Page 22 of 30
Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
REGISTER DEFINITIONS
Register format
Bit Global Address 23:17 R/W 16 Register Address 15:8 Data 7:0
Table 16 Note 1: The format is the same for I2C and SPI. Note 2: Global address for the AD193X series is 0x04, shifted left 1 bit due to the R/W bit. Note 3: In I2C, ADR0 and ADR1 are ORed into bits 17 and 18 to provide multiple chip addressing. Note 4: All registers are reset to 0, except for the DAC volume registers which are set to full volume.
Register addresses and functions
Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Function PLL and Clock Control 0 PLL and Clock Control 1 DAC Control 0 DAC Control 1 DAC Control 2 DAC Individual Channel Mutes DAC 1L Vol Control DAC 1R Vol Control DAC 2L Vol Control DAC 2R Vol Control DAC 3L Vol Control DAC 3R Vol Control DAC 4L Vol Control DAC 4R Vol Control ADC Control 0 ADC Control 1 ADC Control 2
Table 17
Rev. PrI | Page 23 of 30
AD1935/AD1936/AD1937/AD1938/AD1939
PLL AND CLOCK CONTROL REGISTERS
PLL and Clock control 0
Bit 0 2:1 Value 0 1 00 01 10 11 00 01 10 11 00 01 10 11 0 1 Function Normal operation Power down INPUT 256 (x 44.1 or 48kHz) INPUT 384 (x 44.1 or 48kHz) INPUT 512 (x 44.1 or 48kHz) INPUT 768 (x 44.1 or 48kHz) XTAL Oscillator Enabled 256xfs VCO Output 512xfs VCO Output Off MCLK DLRCLK ALRCLK Reserved Disable: ADC and DAC Idle Enable: ADC and DAC Active Description PLL power down
Preliminary Technical Data
MCLK pin functionality (PLL active)
4:3
MCLK_O pin
6:5
PLL input
7
Internal MCLK Enable
Table 18
PLL and Clock control 1
Bit 0 1 2 3 7:4 Value 0 1 0 1 0 1 0 1 0000 Function PLL Clock MCLK PLL Clock MCLK Enabled Disabled Not Locked Locked Reserved Description DAC Clock Source Select ADC Clock Source Select On-chip Voltage Reference PLL Lock Indicator (Read Only)
Table 19
Rev. PrI | Page 24 of 30
Preliminary Technical Data
DAC CONTROL REGISTERS
DAC control 0
Bit 0 2:1 Value 0 1 00 01 10 11 000 001 010 011 100 101 110 111 00 01 10 11 Function Normal Power down 32/44.1/48 kHz 64/88.2/96 kHz 128/176.4/192 kHz Reserved 1 0 8 12 16 Reserved Reserved Reserved Stereo (Normal) TDM (Daisy Chain) DAC Aux mode (ADC, DAC TDM coupled) Dual-line TDM
AD1935/AD1936/AD1937/AD1938/AD1939
Description Power Down Sample Rate
5:3
SDATA Delay (BCLK periods)
7:6
Serial Format
Table 20
DAC control 1
Bit 0 2:1 Value 0 1 00 01 10 11 0 1 0 1 0 1 0 1 0 1 Function Latch in mid cycle (normal) Latch in at end of cycle (pipeline) 64 (2 channels) 128 (4 channels) 256 (8 channels) 512 (16 channels) Left low Left high Slave Master Slave Master DBCLK pin Internally generated Normal Inverted Description BCLK Active Edge (TDM In) BCLKs Per Frame
3 4 5 6 7
LRCLK Polarity LRCLK Master/Slave BCLK Master/Slave BCLK Source BCLK Polarity
Table 21
Rev. PrI | Page 25 of 30
AD1935/AD1936/AD1937/AD1938/AD1939
DAC control 2
Bit 0 2:1 Value 0 1 00 01 10 11 00 01 10 11 0 1 00 Function Unmute Mute Flat 48 kHz Curve 44.1 kHz Curve 32 kHz Curve 24 20 Reserved 16 Non-inverted Inverted Reserved Description Master Mute
Preliminary Technical Data
Deemphasis (32/44.1/48 kHz mode only)
4:3
Word width
5 7:6
DAC Output Polarity
Table 22
DAC Individual Channel Mutes
Bit 0 1 2 3 4 5 6 7 Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Unmute Mute Unmute Mute Unmute Mute Unmute Mute Unmute Mute Unmute Mute Unmute Mute Unmute Mute Description DAC 1 Left Mute DAC 1 Right Mute DAC 2 Left Mute DAC 2 Right Mute DAC 3 Left Mute DAC 3 Right Mute DAC 4 Left Mute DAC 4 Right Mute
Table 23
DAC Volume Controls
Bit 7:0 Value 0 1-254 255 Function No attenuation -3/8 dB per step Full Attenuation Description DAC Volume Control
Table 24
Rev. PrI | Page 26 of 30
Preliminary Technical Data
ADC CONTROL REGISTERS
ADC control 0
Bit 0 1 2 3 4 5 7:6 Value 0 1 0 1 0 1 0 1 0 1 0 1 00 01 10 11 Function Normal Power down Off On Unmute Mute Unmute Mute Unmute Mute Unmute Mute 32/44.1/48 64/88.2/96 128/176.4/192 Reserved
AD1935/AD1936/AD1937/AD1938/AD1939
Description Power Down Highpass Filter ADC 1L mute ADC 1R mute ADC 2L mute ADC 2R mute Output Sample Rate
Table 25
ADC control 1
Bit 1:0 Value 00 01 10 11 000 001 010 011 100 101 110 111 00 01 10 11 0 1 Function 24 20 Reserved 16 1 0 8 12 16 Reserved Reserved Reserved Stereo TDM (Daisy Chain) ADC Aux mode (ADC, DAC TDM coupled) Reserved Latch in mid cycle (normal) Latch in at end of cycle (pipeline)
Table 26.
Description Word width
4:2
SDATA delay (BCLK periods)
6:5
Serial Format
7
BCLK Active Edge (TDM In)
Rev. PrI | Page 27 of 30
AD1935/AD1936/AD1937/AD1938/AD1939
ADC control 2
Bit 0 1 2 3 5:4 Value 0 1 0 1 0 1 0 1 00 01 10 11 0 1 0 1 Function 50/50 (allows 32/24/20/16 BCLK/channel) Pulse (32 BCLK/channel) Drive out on falling edge (DEF) Drive out on rising edge Left Low Left High Slave Master 64 128 256 512 Slave Master ABCLK pin Internally generated
Table 27
Preliminary Technical Data
Description LRCLK Format BCLK Polarity LRCLK Polarity LRCLK Master/Slave BCLKs per frame
6 7
BCLK Master/Slave BCLK Source
Rev. PrI | Page 28 of 30
Preliminary Technical Data OUTLINE DIMENSIONS
0.75 0.60 0.45
AD1935/AD1936/AD1937/AD1938/AD1939
1.60 MAX
48 1
9.00 BSC SQ
37 36
PIN 1
1.45 1.40 1.35
TOP VIEW
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
(PINS DOWN)
7.00 BSC SQ
0.15 0.05
12 13 24
25
SEATING PLANE
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
VIEW A
0.50 BSC LEAD PITCH
0.27 0.22 0.17
Figure 29. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters
Figure 30. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64) Dimensions shown in millimeters
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrI | Page 29 of 30
AD1935/AD1936/AD1937/AD1938/AD1939
Ordering Guide
AD193X Products AD1935XSTZ AD1935XSTZRL AD1936XSTZ AD1936XSTZRL AD1937XSTZ AD1937XSTZRL AD1938XSTZ AD1938XSTZRL AD1939XSTZ AD1939XSTZRL EVAL-AD1935EB EVAL-AD1936EB EVAL-AD1937EB EVAL-AD1938EB EVAL-AD1939EB Temperature Package (ambient) -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C
Preliminary Technical Data
Package Description 64-Lead LQFP, SE out, SPI control w/ reg 64-Lead LQFP, SE out, SPI control w/ reg 48-Lead LQFP, SE out, I2C control 48-Lead LQFP, SE out, I2C control 64-Lead LQFP, Diff out, I2C control 64-Lead LQFP, Diff out, I2C control 48-Lead LQFP, SE out, SPI control 48-Lead LQFP, SE out, SPI control 64-Lead LQFP, Diff out, SPI control 64-Lead LQFP, Diff out, SPI control AD1935 Evaluation Board AD1936 Evaluation Board AD1937 Evaluation Board AD1938 Evaluation Board AD1939 Evaluation Board
Package Option ST-64 ST-64 on 13" Reels ST-48 ST-48 on 13" Reels ST-64 ST-64 on 13" Reels ST-48 ST-48 on 13" Reels ST-64 ST-64 on 13" Reels
Note: All parts are lead-free
Table 28. Ordering Guide
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. Printed in the U.S.A. PR05582-0-5/05(PrI)
Rev. PrI | Page 30 of 30

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